top of page

   CMOS Design & Verification

       Class: T Y B Tech (E&TC) 


   Academic Year 2024-25 Sem-II

Course Outcomes (COs):

 

CO1: Simulate various digital systems using HDL.

 

CO2: Demonstrate structural effects analysis in MOSFET.

CO3: Construct digital logic circuits using CMOS logic .

 

CO4: Construct   layout of various CMOS circuits.

 

CO5: Describe effect of various performance parameters of CMOS inverter.

 

CO6: Apply knowledge of issues and testability in digital design.

Innovative Teaching learning 

1) You Tube Channel 

2) Microsoft Forms

3) Deldsim Tool

4) Tinker CAD Tool

5) NPTEL Videos

6) Moodle

09970063553

  • Facebook
  • Twitter
  • LinkedIn

©2022 by JSPM's RSCOE Tathawade Pune. Proudly created with Wix.com

bottom of page