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International Journal 

  1. Paper published in International Advanced Research Journal in Science, Engineering and Technology  (IARJSET) Title “Simulation of Graded Channel Double Gate Junctionless Transistor for Low Power and High Performance” Vol.09, No.4, April 2022, pp. 251-260, ISSN: 2393-8021, Publisher : International Advanced Research Journal in Science, Engineering and Technology.

  2. Paper published in International Journal of International Journal of Engineering and Advanced Technology (IJEAT) Title “ Performance Analysis of CMOS Circuits using Shielded Channel Dual Gate Stack Silicon on Nothing Junctionless Transistor” Vol.10, No.6, Aug 2021, pp. 1-10, ISSN: 2249-8958, Publisher : Blue Eyes Intelligence Engineering and Sciences Publication.

  3. Paper published in International Journal of International Journal of Advances in Engineering and Management, Title: “IOT based home automation system using FPGA”, Vol.3, No.7, July 2021, pp 2180-2182, ISSN: 2395-5252, Publisher: IJAEM.

  4. Paper published in International journal of electronics letters,  Title: “Nanoscale Shielded Channel Dual Gate Stack Silicon on nothing Junctionless Transistor for Improving Short Channel Effect and Analog Performance” Journal: International journal of electronics letters, Vol 8 No-1, pp.97-114, 2020 ISSN: 2168-1724  Publisher: Taylor and Francis.

  5. Paper published in International Journal of International Journal for research & Development in Technology Title  “Design and FPGA Implementation of of 8 Bit Vedic Multiplier” Volume-11,No-06, June 2019, ISSN No-2349-3585.

  6. Paper Published in International Journal of Materials, Mechanics and Manufacturing, Title “Comparison study of Dual Material Gate Silicon on Insulator junctionless Transistor and with Junction Transistor for Analog Performance” Vol.07, No.3, pp.144-149, Jun 2019, ISSN: 1793:8198, Publisher: IJMMM.

  7. Paper published in International Journal of Indonesian Journal of Electrical Engineering and Informatics Title “Analytical Current Model for Dual Material Double Gate Junctionless Transistor” Vol-07, No-3, Sep 2019, pp 555-563, ISSN 2089:3272. Publisher: Institute of Advanced Engineering and science.

  8. Paper published in International journal of electronics on 14 Jan 2019 Title: “Dual Material Gate Silicon on Insulator Junctionless MOSFET for Low Power Mixed Signal Circuits” Authors: S.C. Wagaj, S.C.Patil Journal: International journal of electronics, Vol 107, No.7, 2019, pp 992-1007, ISSN: 0020-7217 Publisher: Taylor and Francis.

  9. Paper published in International Journal for Scientific Research & Development| Vol. 6, Issue 08, 2018, ISSN (online): 2321-0613, Title “Road Accidents Prevention System using Driver's Drowsiness Detection”.

  10. Paper published in International Journal of creative Research Thoughts Vol.6, issue 2, April 2018, ISSN: 2320-2882, Title “Comparative Study of Dual Material Asymmetric Double Gate Junctionless and Junction Transistor”.

  11. Publish paper in International Journal of Engineering science and computing title “Implementation of Advanced Encryption Standard (AES) on FPGA”, Vol.7, Issue no.5, ISSN 2250-1371, May 2017.

  12. Publish paper in International Journal of Electronics Letters (Taylor & Francis) title” Performance Analysis of Schielded Channel Double Gate Junctionless and Junction MOS-Transistor” June 2017.

  13. Publish paper in International Organization of Scientific Research  title “Effect of Process Parameters Variations on Dual Material Gate SOI Junctionless Transistor “Journal of Electronics and Communication Engineering( IOSR-JECE), e-ISSN:2278-2834, P-ISSN:2278-8735, pp.93-99, 2015.

  14. Publish paper in International Organization of Scientific Research title “Health Monitoring System Using PSOC”, and publish paper in NCIEST-2015 organized by JSPM’s Rajarshi Shahu College of Engineering Tathawade pune on 28th and 29th December 2015.

  15. Published American International Journal of Research in science, Technology, Engineering and Mathematics title “A Review paper: A comprehensive study of Junctionless MOSFETs”, ISSN-2328-3491, Vol-1, Issue-12, November 2015, pp-40-47.

  16. Published International Journal of science and Research title “Review: Health Monitoring System”,ISSN (online) 2319-7064,volume 4, Issue 10,oct-2015.

  17. Published a research paper “A Review: SIFT Hardware Implementation for Real Time Feature Extraction” in IJAREEIE, volume 4,Issue 4, April 2015.

  18. Paper publishes in International Journal of Advanced Technology in Engineering and Science ISSN-2348-7550.VOL-3 Issue-1, Jan 2015.” Convolution Encoding and Viterbi Decoding Based on FPGA using VHDL” .

  19. Paper publish in International Journal of Advanced Technology in Engineering and Science ISSN-2348-7550.Vol-3 Issue-1, Jan 2015.” FPGA Based Network Security Using RC5 Algorithm”,

  20. Paper publish in International Journal of Advanced Research (ISSN(print):2249-7277 ISSN(online):2277-7970) Volume-3 Number-3 Issue-11, pp. 201-204,  September 2013 Title of paper “Implementation of RC4 Stream Cipher Using FPGA”

Research Projects

  1. Working on research funded by Board of College and University Development of  Savitribai Phule pune  University research title “Design and Modeling of Silicon Carbide MOSFETs for High Performance Mixed-Signal Circuits”  in Academic year 2013-14.

  2. Working on research funded by Board of College and University Development of Savitribai Phule pune University research title “Obstacal detection by ROBOT”  in Academic year 2014-15.

  3. Research project fund received from BCUD of Savitribai Phule Pune University title of project “Design and Modeling of Multi Material gate Junctionless MOSFET for High performace Mixed signal circuits”, in academic year 2016-17

Patent Published

1) Title:”Design and Implementation of Shielded channel Double Gate Junctionless Metal Oxide Semiconductor Transistor for low Power and High Performance” Publication date: 15/01/2016.

 

2)  Title “Design and Implementation of Nanoscale dual gate stack silicon on nothing junctionless transistor for improving short channel effect and performance, publication date 15/09/2017.

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